Apparatus and method including neural network learning to detect and correct quantum errors

ABSTRACT

Apparatus and method for neural network learning to detect and correct quantum errors. For example, one embodiment of an apparatus comprises. For example, one embodiment of an apparatus comprises: a quantum processor comprising one or more data quantum bits (qbits) and one or more ancilla qbits; an error decoder to decode a state of at least one of the ancilla qbits to generate an error syndrome related to one or more qbit errors; a neural network to evaluate the error syndrome and to either identify a known corrective response for correcting the error or to perform unsupervised learning to identify a corrective response to the error syndrome.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of co-pending U.S. patent applicationSer. No. 15/972,114, filed on May 5, 2018.

BACKGROUND Field of the Invention

The embodiments of the invention relate generally to the field ofquantum computing. More particularly, these embodiments relate to anapparatus and method including neural network learning to detect andcorrect quantum errors.

Description of the Related Art

Quantum computing refers to the field of research related to computationsystems that use quantum mechanical phenomena to manipulate data. Thesequantum mechanical phenomena, such as superposition (in which a quantumvariable can simultaneously exist in multiple different states) andentanglement (in which multiple quantum variables have related statesirrespective of the distance between them in space or time), do not haveanalogs in the world of classical computing, and thus cannot beimplemented with classical computing devices.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained from thefollowing detailed description in conjunction with the followingdrawings, in which:

FIGS. 1A-1F illustrate various views of an example quantum dot device,in accordance with one embodiment;

FIG. 2 illustrates one embodiment of a quantum controller formaintaining and utilizing an activity map to reduce heating within aquantum processor;

FIG. 3 illustrates another embodiment of a quantum controller formaintaining and utilizing an activity map to reduce heating within aquantum processor;

FIG. 4 illustrates a method in accordance with one embodiment of theinvention;

FIG. 5 illustrates a sequence of operations for performing errorcorrection;

FIG. 6 illustrates one embodiment of a quantum controller using a neuralnetwork such as a neuromorphic processor;

FIG. 7 illustrates additional details of one embodiment of the quantumcontroller;

FIG. 8 illustrates one embodiment of a method for detecting andcorrecting errors;

FIG. 9 is a block diagram illustrating an exemplary neuromorphicprocessor architecture;

FIG. 10 illustrates one embodiment of a neuromorphic processor whichincludes spike controllers for generating trigger signals;

FIG. 11 illustrates one embodiment of a neuromorphic core; and

FIG. 12 illustrates one embodiment of a spike controller.

DETAILED DESCRIPTION

In the following description, for the purposes of explanation, numerousspecific details are set forth in order to provide a thoroughunderstanding of the embodiments of the invention described below. Itwill be apparent, however, to one skilled in the art that theembodiments of the invention may be practiced without some of thesespecific details. In other instances, well-known structures and devicesare shown in block diagram form to avoid obscuring the underlyingprinciples of the embodiments of the invention.

INTRODUCTION

A quantum computer uses quantum-mechanical phenomena such assuperposition and entanglement to perform computations. In contrast todigital computers which store data in one of two definite states (0 or1), quantum computation uses quantum bits (qbits), which can be insuperpositions of states. Qbits may be implemented using physicallydistinguishable quantum states of elementary particles such as electronsand photons. For example, the polarization of a photon may be used wherethe two states are vertical polarization and horizontal polarization.Similarly, the spin of an electron may have distinguishable states suchas “up spin” and “down spin.”

Qbit states are typically represented by the bracket notations |0> and|1>. In a traditional computer system, a bit is exclusively in one stateor the other, i.e., a ‘0’ or a ‘1.’ However, qbits in quantum mechanicalsystems can be in a superposition of both states at the same time, atrait that is unique and fundamental to quantum computing.

Quantum computing systems execute algorithms containing quantum logicoperations performed on qubits. The sequence of operations is staticallycompiled into a schedule and the qubits are addressed using an indexingscheme. This algorithm is then executed a sufficiently large number oftimes until the confidence interval of the computed answer is above athreshold (e.g., ˜95+%). Hitting the threshold means that the desiredalgorithmic result has been reached.

Qbits have been implemented using a variety of different technologieswhich are capable of manipulating and reading quantum states. Theseinclude, but are not limited to quantum dot devices (spin based andspatial based), trapped-ion devices, superconducting quantum computers,optical lattices, nuclear magnetic resonance computers, solid-state NMRKane quantum devices, electrons-on-helium quantum computers, cavityquantum electrodynamics (CQED) devices, molecular magnet computers, andfullerene-based ESR quantum computers, to name a few. Thus, while aquantum dot device is described below in relation to certain embodimentsof the invention, the underlying principles of the invention may beemployed in combination with any type of quantum computer including, butnot limited to, those listed above. The particular physicalimplementation used for qbits is orthogonal to the embodiments of theinvention described herein.

QUANTUM DOT DEVICES

Quantum dots are small semiconductor particles, typically a fewnanometers in size. Because of this small size, quantum dots operateaccording to the rules of quantum mechanics, having optical andelectronic properties which differ from macroscopic entities. Quantumdots are sometimes referred to as “artificial atoms” to connote the factthat a quantum dot is a single object with discrete, bound electronicstates, as is the case with atoms or molecules.

FIGS. 1A-1F are various views of a quantum dot device 100, which may beused with embodiments of the invention described below. FIG. 1A is a topview of a portion of the quantum dot device 100 with some of thematerials removed so that the first gate lines 102, the second gatelines 104, and the third gate lines 106 are visible. Although many ofthe drawings and description herein may refer to a particular set oflines or gates as “barrier” or “quantum dot” lines or gates,respectively, this is simply for ease of discussion, and in otherembodiments, the role of “barrier” and “quantum dot” lines and gates maybe switched (e.g., barrier gates may instead act as quantum dot gates,and vice versa). FIGS. 1B-1F are side cross-sectional views of thequantum dot device 100 of FIG. 1A; in particular, FIG. 1B is a viewthrough the section B-B of FIG. 1A, FIG. 1C is a view through thesection C-C of FIG. 1A, FIG. 1D is a view through the section D-D ofFIG. 1A, FIG. 1E is a view through the section E-E of FIG. 1A, and FIG.1F is a view through the section F-F of FIG. 1A.

The quantum dot device 100 of FIG. 1 may be operated in any of a numberof ways. For example, in some embodiments, electrical signals such asvoltages, currents, radio frequency (RF), and/or microwave signals, maybe provided to one or more first gate line 102, second gate line 104,and/or third gate line 106 to cause a quantum dot (e.g., an electronspin-based quantum dot or a hole spin-based quantum dot) to form in aquantum well stack 146 under a third gate 166 of a third gate line 106.Electrical signals provided to a third gate line 106 may control theelectrical potential of a quantum well under the third gates 166 of thatthird gate line 106, while electrical signals provided to a first gateline 102 (and/or a second gate line 104) may control the potentialenergy barrier under the first gates 162 of that first gate line 102(and/or the second gates 164 of that second gate line 104) betweenadjacent quantum wells. Quantum interactions between quantum dots indifferent quantum wells in the quantum well stack 146 (e.g., underdifferent quantum dot gates) may be controlled in part by the potentialenergy barrier provided by the barrier potentials imposed between them(e.g., by intervening barrier gates).

Generally, the quantum dot devices 100 disclosed herein may furtherinclude a source of magnetic fields (not shown) that may be used tocreate an energy difference in the states of a quantum dot (e.g., thespin states of an electron spin-based quantum dot) that are normallydegenerate, and the states of the quantum dots (e.g., the spin states)may be manipulated by applying electromagnetic energy to the gates linesto create quantum bits capable of computation. The source of magneticfields may be one or more magnet lines, as discussed below. Thus, thequantum dot devices 100 disclosed herein may, through controlledapplication of electromagnetic energy, be able to manipulate theposition, number, and quantum state (e.g., spin) of quantum dots in thequantum well stack 146.

In the quantum dot device 100 of FIG. 1, a gate dielectric 114 may bedisposed on a quantum well stack 146. A quantum well stack 146 mayinclude at least one quantum well layer 152 (not shown in FIG. 1) inwhich quantum dots may be localized during operation of the quantum dotdevice 100. The gate dielectric 114 may be any suitable material, suchas a high-k material. Multiple parallel first gate lines 102 may bedisposed on the gate dielectric 114, and spacer material 118 may bedisposed on side faces of the first gate lines 102. In some embodiments,a patterned hardmask 110 may be disposed on the first gate lines 102(with the pattern corresponding to the pattern of the first gate lines102), and the spacer material 118 may extend up the sides of thehardmask 110, as shown. The first gate lines 102 may each be a firstgate 162. Different ones of the first gate lines 102 may be electricallycontrolled in any desired combination (e.g., each first gate line 102may be separately electrically controlled, or some or all the first gatelines 102 may be shorted together in one or more groups, as desired).

Multiple parallel second gate lines 104 may be disposed over and betweenthe first gate lines 102. As illustrated in FIG. 1, the second gatelines 104 may be arranged perpendicular to the first gate lines 102. Thesecond gate lines 104 may extend over the hardmask 110, and may includesecond gates 164 that extend down toward the quantum well stack 146 andcontact the gate dielectric 114 between adjacent ones of the first gatelines 102, as illustrated in FIG. 1D. In some embodiments, the secondgates 164 may fill the area between adjacent ones of the first gatelines 102/spacer material 118 structures; in other embodiments, aninsulating material (not shown) may be present between the first gatelines 102/spacer material 118 structures and the proximate second gates164. In some embodiments, spacer material 118 may be disposed on sidefaces of the second gate lines 104; in other embodiments, no spacermaterial 118 may be disposed on side faces of the second gate lines 104.In some embodiments, a hardmask 115 may be disposed above the secondgate lines 104. Multiple ones of the second gates 164 of a second gateline 104 are electrically continuous (due to the shared conductivematerial of the second gate line 104 over the hardmask 110). Differentones of the second gate lines 104 may be electrically controlled in anydesired combination (e.g., each second gate line 104 may be separatelyelectrically controlled, or some or all the second gate lines 104 may beshorted together in one or more groups, as desired). Together, the firstgate lines 102 and the second gate lines 104 may form a grid, asdepicted in FIG. 1.

Multiple parallel third gate lines 106 may be disposed over and betweenthe first gate lines 102 and the second gate lines 104. As illustratedin FIG. 1, the third gate lines 106 may be arranged diagonal to thefirst gate lines 102, and diagonal to the second gate lines 104. Inparticular, the third gate lines 106 may be arranged diagonally over theopenings in the grid formed by the first gate lines 102 and the secondgate lines 104. The third gate lines 106 may include third gates 166that extend down to the gate dielectric 114 in the openings in the gridformed by the first gate lines 102 and the second gate lines 104; thus,each third gate 166 may be bordered by two different first gate lines102 and two different second gate lines 104. In some embodiments, thethird gates 166 may be bordered by insulating material 128; in otherembodiments, the third gates 166 may fill the openings in the grid(e.g., contacting the spacer material 118 disposed on side faces of theadjacent first gate lines 102 and the second gate lines 104, not shown).Additional insulating material 117 may be disposed on and/or around thethird gate lines 106. Multiple ones of the third gates 166 of a thirdgate line 106 are electrically continuous (due to the shared conductivematerial of the third gate line 106 over the first gate lines 102 andthe second gate lines 104). Different ones of the third gate lines 106may be electrically controlled in any desired combination (e.g., eachthird gate line 106 may be separately electrically controlled, or someor all the third gate lines 106 may be shorted together in one or moregroups, as desired).

Although FIGS. 1A-F illustrate a particular number of first gate lines102, second gate lines 104, and third gate lines 106, this is simply forillustrative purposes, and any number of first gate lines 102, secondgate lines 104, and third gate lines 106 may be included in a quantumdot device 100. Other examples of arrangements of first gate lines 102,second gate lines 104, and third gate lines 106 are possible. Electricalinterconnects (e.g., vias and conductive lines) may contact the firstgate lines 102, second gate lines 104, and third gate lines 106 in anydesired manner.

Not illustrated in FIG. 1 are accumulation regions that may beelectrically coupled to the quantum well layer of the quantum well stack146 (e.g., laterally proximate to the quantum well layer). Theaccumulation regions may be spaced apart from the gate lines by a thinlayer of an intervening dielectric material. The accumulation regionsmay be regions in which carriers accumulate (e.g., due to doping, or dueto the presence of large electrodes that pull carriers into the quantumwell layer), and may serve as reservoirs of carriers that can beselectively drawn into the areas of the quantum well layer under thethird gates 166 (e.g., by controlling the voltages on the quantum dotgates, the first gates 162, and the second gates 164) to formcarrier-based quantum dots (e.g., electron or hole quantum dots,including a single charge carrier, multiple charge carriers, or nocharge carriers). In other embodiments, a quantum dot device 100 may notinclude lateral accumulation regions, but may instead include dopedlayers within the quantum well stack 146. These doped layers may providethe carriers to the quantum well layer. Any combination of accumulationregions (e.g., doped or non-doped) or doped layers in a quantum wellstack 146 may be used in any of the embodiments of the quantum dotdevices 100 disclosed herein.

APPARATUS AND METHOD INCLUDING A THERMAL NOISE ADAPTIVE SCHEDULER FORCONTROLLING A QUANTUM COMPUTER

Regardless of the manner in which qbits are implemented, continuousoperation of a quantum computer requires maintenance of the quantuminformation contained in the qubits over long sequences of gateoperations. For example, when quantum operations are implemented usingmicrowave pulses that manipulate or read the qubits, there is acontinual need to dissipate heat. Over repeated algorithm runs, thermalheating results in a more rapid loss of quantum information throughdecoherence, stark shift induced loss of gate fidelity, and degradationof system performance until a recalibration cycle is needed. Currentmitigation efforts focus on minimizing the algorithm circuit depth,capping RF radiation to the dissipation rate of the refrigeration unit,or leaving the problem to the future.

One embodiment of the invention implements a dynamic scheduling modulethat reorders qubit addressing and circuit scheduling operations bymaintaining an activity map (or “heat map”) of a qubit plane duringcontinuous operation of the quantum computer. While the embodiments ofthe invention described here track operations in a 2D plane, theunderlying principles of the invention are not limited to a 2D trackingarrangement. For example, activity maps may also be implemented for 1Dor 3D qbit arrangements.

FIG. 2 illustrates an exemplary quantum computing architecture in whichqbits 265 of a quantum processor 260 are manipulated in response tosignals from a quantum controller 205. Any type of qbits 265 may be usedwithin the quantum processor 260 including, by way of example, and notlimitation, trapped ion qbits and quantum dots. In one embodiment, thequantum controller 205 implements a quantum runtime 201 specified by aprogrammer. For example, the quantum runtime 201 may comprise softwareexecuted on a general purpose processor. The quantum controller 205 mayinclude both a general purpose processor to execute software andspecialized circuitry to control the qbits (certain aspects of which aredescribed herein). In response to execution of the quantum runtime code201, the quantum processor 260 performs operations on the qbits 265 togenerate results 270. In one implementation, multiple iterations of aparticular operation or series of operations are required to generatethe results 270.

In one embodiment, an arbiter 220 monitors access to the qbits 265 inaccordance with the quantum runtime code 201 and updates an activity map210 stored in a storage device 211 on the quantum controller 205. Theactivity map 210 may be updated in accordance with the frequency withwhich operations are performed on each of the qbits 265. In oneembodiment, for example, an activity value associated with each qbit isincremented by an amount proportional to the pulse energy applied tothat qbit and is decremented periodically (e.g., based on a heatdissipation rate associated with the system). In this implementation,the activity map 210 includes an identifier associated with each qbit(e.g., the qbit's virtual or physical address) and a current activityvalue which is continually updated based on pulse frequency and the heatdissipation rate. The activity map 210 may also be referred to as a heatmap because it displays the heat produced in each region of the quantumprocessor 260 and/or surrounding each qbit 265.

In one embodiment, the arbiter 220 uses the above techniques to detectexcessive heating and signals the adaptive scheduler 230 to move qubitsto different regions to spread the heat more evenly. The adaptivescheduler 230 then configures and schedules operations on each of theqbits 265 based on the activity map 210. For example, if the activitymap indicates that a particular qbit or region of qbits has significantrecent activity (indicating a higher temperature), then the scheduler230 may redirect operations to a new set of qbits 265 in a differentregion of the quantum processor 260. For example, in one embodiment, theadaptive scheduler 230 changes the physical quantum gates being used ifthe activity map 210 indicates that the current set of quantum gateshave potentially become noisier due to heating.

One or more physical layer devices 240 perform the underlying operationson the qbits 265 as specified by the quantum runtime 201. For example,the physical layer devices 240 may include electromagnetic transmittersto generate microwave pulses or other electromagnetic pulses tomanipulate the qbits 265.

FIG. 3 illustrates an alternate embodiment in which the physical layerdevices 240 are integrated within the quantum processor rather than thequantum controller 205. In this embodiment, the quantum controller 205is communicatively coupled to the physical layer devices 240 of thequantum processor 260 over one or more serial communicationinterconnects (e.g., a Universal Serial Bus or comparable serialinterface) or network interconnects (e.g., Ethernet, WiFi, etc). Ofcourse, the underlying principles of the invention are not limited toany particular arrangement of the physical layer devices 240 or theparticular communication protocol for coupling the quantum controller205 to the quantum processor 260.

In one embodiment, the results 270 of the qbit operations are stored ina database, file system, or other form of data storage structure. Whileillustrated separately from the quantum runtime 201 and quantumcontroller 205, the results 270, quantum controller 205 and quantumruntime 201 may all be implemented on the same physical computing devicesuch as a server or workstation with a memory, at least one processor, astorage device and a serial and/or wireless communication interfaces tocouple the quantum controller 205 to a network.

As indicated in FIGS. 2-3, one embodiment of the quantum runtime 201transmits operations to the quantum controller 205 in accordance withthe Open Quantum Assembly Language (QASM), an intermediaterepresentation for quantum instructions. However, the underlyingprinciples of the invention are not limited to any particular language.

In one embodiment, the adaptive scheduler 230 is coupled to (orincludes) a translation lookaside buffer (TLB) 232 to translate virtualqbit addresses to physical qbit addresses which identify the physicallayer device 240 to access each of the qbits 265. In one implementation,the adaptive scheduler changes physical qubit addressing within the TLB232 in accordance with the activity map 210 to ensure that a particularset of one or more qbits 265 are not over-utilized. For example, theadaptive scheduler 230 may associate new physical addresses for a newset of qbits 265 with existing virtual addresses in the TLB 232, therebyspreading the heat more evenly across the qbits 265.

A method in accordance with one embodiment is illustrated in FIG. 4. Themethod may be implemented on the specific architectures described above,but is not limited to any particular quantum architecture.

At 401 an arbiter tracks operation pulse energy applied at each qbitaddress over time in an activity map structure. As mentioned, theactivity map is read to determine whether excessive heating has occurredwith respect to a particular set of quantum gates/qbits. For example, ifa particular gate/qbit has been energized above a specified thresholdwithin a specified period of time, then excessive heating is determinedat 402. As a result, at 403 the arbiter signals to the adaptivescheduler to move qbits based on the activity map. At 404, the adaptivescheduler changes physical qbit addressing via a TLB to ensurecontinuous operation, changing the physical quantum gates if necessarydue to heating. At 405, the adaptive scheduler injects the quantumoperations into the quantum processor which performs the operations andgenerates results 270.

As a result of the reduction in heating associated with each gate/qbit,the embodiments of the invention increase up-time of a quantum computerfor continuous algorithm execution. For example, the need forrecalibration cycles is reduced, thereby providing a performanceadvantage over existing systems. Larger circuit depth algorithms mayalso be executed, resulting in longer calculations.

ADAPTIVE ERROR CORRECTION AND CONTROL OF A QUANTUM COMPUTER USING ASPIKING NEURAL NET

Qubits are fragile and respond to various sources of noise whichintroduces challenges in scalability to large numbers of physicalqubits. Quantum Error Correction for quantum computers is implemented byencoding a logical qubit in a set of physical qubits. These physicalqubits are periodically measured in an error correction cycle and theresults are used to detect whether an error has occurred (e.g., a randomflip of a qubit). The error cycle completes with a correction of theencoding.

The process of detecting errors and classifying them to enablecorrection is complex and expensive in execution time and energy. Somealternative approaches using Neural Network methods are being proposedin order to reduce these costs. However, none of the proposed methodsadapt to changing error behavior over the life cycle of the chip. Mostrequire the choice of encoding to be set at design time and remain fixedthrough the operation of the device.

One embodiment of the invention uses a particular form of neural networkimplementation as embodied in a neuromorphic chip which is more energyefficient than a conventional neural network implemented in software orhardware. FIG. 7 (described below) illustrates an example neuromorphicarchitecture with which embodiments of the invention may be implemented.

During breaks in the normal computation cycle of the quantum computer,diagnostic workloads are executed for which correct outcomes are known.The spiking neural network within the neuromorphic processor then usesthe results of the algorithmic runs combined with the Quantum ErrorCorrection cycle measurements to detect new types of errors discoveredin the system and continually retrain itself to classify and correct forthis new source of error.

Existing neural network based approaches focus on large training datasets that have been generated for specific types of errors that theyexpect to encounter in a quantum system of a specific size. Theseapproaches require a large up-front investment in tuning the trainingdata to catch a large percentage of errors whereas the embodiments ofthe invention adapt dynamically both to the specific quantum processorbeing used and continuously learn and adapts as new errors appear ineach individual system over time. This also results in a more efficientneural network which does not have sensitivity to the training data setand thus does not store redundant sources of errors that have a lowprobability of ever occurring. A spiking neural network based learningapproach as represented by the example neuromorphic processor describedbelow is also likely to be highly more energy efficient because thenetwork only encodes errors it has actually encountered; consequently,less computation is required to parse a large training data set. Thetypes of errors that the system can correct for is also expanded toerror propagation in quantum circuits because it distinguishestiming-based errors from those encountered when applying a singlequantum operation.

FIG. 5 illustrates one embodiment of a quantum error correction cycle.At 501 the logical qbit state of the system is initialized. For example,if electron spin is used as the quantum state, then electrons within thequantum system may be prepared (e.g., initialized to a particular spinorientation and/or entangled using electromagnetic control signals fromthe quantum controller).

At 502, the state of the quantum system evolves in response toadditional electromagnetic inputs specified by the quantum runtime 201and implemented by the quantum controller 205.

At 503, a measurement of the quantum system is taken. For example, thecurrent spin of one of the entangled electrons may be measured. Thesystem may subsequently be re-initialized prior to the next measurement(i.e., given that taking a measurement or learning any information aboutthe quantum system disrupts the quantum state). The physical qubits maybe periodically measured in an error correction cycle. At 504 errordetection/classification is performed on the measured results todetermine whether an error has occurred (e.g., a random flip of aqubit). The error cycle completes with an error correction operation at505, which attempts to correct any detected errors detected.

FIG. 6 illustrates an exemplary quantum controller 610 for performingquantum error detection and correction on results generated by a quantumprocessor 260. In one embodiment, a neural network 614 performsunsupervised learning of error syndromes through execution of adiagnostic learning cycle during idle cycles of the quantum computer. Inone embodiment, the neural network 614 is a neuromorphic processor butcan be implemented with any circuitry and/or logic capable ofunsupervised learning.

In operation, a decoder 613 takes a multi-qubit measurement from thequantum processor 260 which does not disturb the quantum information inthe encoded state but contains information about the error (as describedin greater detail below). In response, the decoder 613 generates errorsyndrome data from which the neural network 614 may determine theerror(s) that have occurred and take steps to correct the error(s). Inone embodiment, the error syndrome data comprises a stabilizer code suchas a surface code. However, the underlying principles of the inventionmay be implemented on quantum systems using various types of errorsyndrome coding.

Upon evaluating the error syndrome data, the neural network 614 may relyon any previously learned errors to select a response, which ittransmits to the quantum control unit 611. In some cases, the responsemay simply be to reinitialize the qbits and start over. In other cases,however, modifications to the quantum algorithm can be made to stabilizethe region of the quantum processor responsible for the error. In eithercase, a pulse generator & QEC circuit 612 performs the underlyingphysical operations under the control of the quantum control unit 611.For example, the pulse generator & QEC circuit generate electromagneticpulses to adjust the phase of one or more qbits in accordance with thedetected phase error, or to reset the phase/spin of all qbits ifre-initialization is required.

In one implementation, the neural network 614 is configured to learn newerror syndromes as they occur. For example, once the quantum computerenters a quiescent state, a diagnostic mode may be executed in which aspecific set of representative quantum algorithms with known outcomes isexecuted and the results decoded by the decoder 613. When the neuralnetwork 614 detects a deviation from the expected result, it attempts tolearn where in the error correction tile a new error syndrome hasoccurred. These errors could be in the physical operations necessary toimplement the fault tolerant surface code tile. For example, thephysical operations necessary to realize certain logical gates gettranslated into a fixed set of physical operations which may incurerrors.

In such a case, the algorithms may be re-executed on a more robust partof the quantum processor 260. The neural network 614 may then comparethe results to those collected from the more faulty part of the chip.The neural network 614 then retrains itself to recognize this error onthe noisy part of the chip and potentially correct for it.

In addition, the neural network 614 may determine whether it hasimproved the system performance or degraded it through several more runsof the quantum algorithm. If it determines that it has successfullycorrected for a new source of error then it will retain the learning.Otherwise, it will abandon it and continue attempting to learnadditional error sources during the diagnostic process.

FIG. 7 illustrates additional details of one embodiment in which thequantum processor 260 includes a plurality of ancilla qubits 701-704which are used to protect the integrity of the data encoded in the dataqbits 700 (which contain the underlying data resulting from a quantumoperation). In one implementation, the ancilla qubits 701-704 can bemeasured without disturbing the quantum information encoded in the dataqbits 700 but can still provide information about the error(s) in thedata qbit(s). In particular, the error syndrome data from the ancillaqbits 701-704 can be used to determine whether a data qubit 700 has beencorrupted, and if so, which one. Further, the error syndrome codeproduced by the decoder 613 in response to reading the ancilla qbits701-704 can identify not only the physical qubit which was affected, butalso in which of several possible ways it was affected.

Two types of ancilla qbits are illustrated in FIG. 7, X-syndrome qbits701-702 and Z-syndrome qbits 703-704, which are used to differentiatebetween phase-flip syndromes (or X-syndromes) and bit-flip syndromes (orZ-syndromes), respectively. In the illustrated embodiment, each dataqubit 700 is coupled with two X-syndrome qubits 701-702 and twoZ-syndrome qubits 703-704. Moreover, each syndrome qubit 701-704 iscoupled with four code qubits 700 (only one of which is illustrated forsimplicity). In one embodiment, the X-syndrome qbits are associated witha bit-flip error and the Z-syndrome qbits are associated with aphase-flip error. However, the underlying principles of the inventionare not limited to any particular coding scheme.

Regardless of the specific type of coding used, the decoder 613generates an error syndrome code 714 in response to reading the ancillaqbits 701-703 and error analysis 715 is performed in the neural network614 to classify and correct the detected error(s) using previouslylearned models 720. For example, if the error syndrome 714 identifies anerror which the error analysis has seen and corrected in the past, thenit will send control/correction data 725 informing the quantum controlunit 611 of the sequence of operations required to correct the error.The quantum control unit 611 will then cause the pulse generator & QECcircuitry 612 to perform the underlying physical operations on the dataqbits 700. For example, in response to two Z-syndrome qbits being out ofparity, the error analysis unit 715 may conclude (based on priorlearning) that a phase flip has occurred on the data qbit 700 hasoccurred. As such, it may send corrective data 725 to the quantumcontrol unit 611 to implement a phase shift on the data qbit 700 set itto the correct phase.

In one embodiment, when the error analysis unit 715 detects an errorsyndrome 714 which it has not seen before, it will attempt to identifyany correlations between the new error syndrome and the learned models720 and will generate control/correction data 725 based on anycorrelation it can identify. After sending the correction data 725, thequantum control unit 611 will cause the recommended correction to beimplemented via the pulse generator & QEC circuit 612. If the correctiverecommendation did not resolve the error, the error analysis unit 715will make another attempt based on the new error syndrome data 714. Forexample, if the recommended correction made the error more pronounced,then it may generate new correction data 725 based on a differentvariable or using an alternate value for a prior variable.

By generating informed corrections and analyzing the results of thosecorrections, the error analysis unit 715 may eventually pinpoint acorrective action which resolves the error encoded in the error syndrome714. Once it does, it stores this new corrective data within the set oflearned models 720 so that it can take immediate corrective action thenext time it sees this particular error syndrome.

Using the above techniques the neural network 614 may performunsupervised learning of new error syndromes 714 as they occur.Unsupervised learning is particularly beneficial for working with aquantum processor 260 because the physical responses of the individualqbits may change over time and may also vary from one quantum processorto another. In one implementation, the neural network 614 is initiallyequipped with a set of basic models 720 which are commonly used todetect and correct certain types of well known errors. Starting withthis base set of models 720, the neural network 624 will continuallytrain itself in response to detecting new error syndromes 714 and updatethe models 720 accordingly. As a result, the neural network 614 willbecome familiar with the particular characteristics of the quantumprocessor 260 with which it is associated and will learn to correctvarious different types of errors, some of which may be unique to thisquantum processor 260.

While the error analysis unit 715 may successfully correct a number ofdifferent errors, some types of errors may be uncorrectable. In thiscase (e.g., after a threshold number of attempts), the error analysisunit 715 may transmit an initialization command to the quantum controlunit 611, which will cause the qbits 700-705 to be re-initialized.

As mentioned, the neural network 614 may be implemented with circuitrysuch as a neuromorphic processor to perform unsupervised learning ofquantum error syndromes. In this embodiment, the error analysis unit 715and learned models 720 are integrated within the neuromorphic processorweighted interconnections between neurons and other data related tothese interconnections. Consequently, the error analysis unit 715 andmodels 720 may not be separate components as shown in FIG. 7 but rathermay be distributed across the neuromorphic processor usinginterconnections and associated weights/data. Moreover, the underlyingprinciples of the invention are not limited to a neuromorphic processorimplementation and may, in fact, be implemented using any processorcapable of unsupervised learning.

A method in accordance with one embodiment is illustrated in FIG. 8. Themethod may be implemented within the context of the quantum systemarchitectures described herein, but is not limited to any particulartype of quantum system.

At 800 the logical states of qbits are initialized on the quantumprocessor and, at 801, quantum operations are executed (e.g., inaccordance with a quantum runtime). As mentioned, the techniquesdescribed herein may be implemented once the quantum computer enters aquiescent state. A diagnostic mode may then be executed in which aspecific set of representative quantum algorithms with known outcomes isexecuted. In addition, these learning techniques may be performed duringnormal system operation.

At 802 the state of the ancilla qbits is read and, at 803, decoded togenerate an error syndrome, if an error is detected. If there is noerror then the process may return to 801 using a different set ofquantum operations. At 804, the error syndrome is evaluated to identifya response, which is then executed. As described above, the response maybe selected by a neuromorphic processor based on existing errorcorrection models. For example, if the error has been seen before, thenthe model will specify the corrective response for this particularerror.

If the corrective response successfully corrects the error, determinedat 805, then at 806, the model may be updated to include data associatedwith the successful corrective response. If the corrective response doesnot correct the error then a determination is made at 807 as to whethera threshold number of error correction attempts have been made. If so,then the qbits are re-initialized at 800. If not, then at 808, a newcorrective response is identified and executed and the process returnsto 805, where a determination is made as to whether the error wascorrected. As indicated in FIG. 8, operations 805-808 compriseunsupervised learning performed by the neural network in one embodiment.

The embodiments described herein may be used to improve fault toleranceand reduce errors in quantum computing systems. Enhanced energyefficiency in providing scalable error correction will also reduce thecost to produce these platforms when compared to heuristic basedapproaches and techniques which rely on large training data sets. Inaddition, unsupervised learning of error conditions will improve theadaptability of quantum computing systems over time and across differentquantum processors.

Current neural network approaches to fault tolerance assume a fixed setof error syndromes across all quantum computing hardwareimplementations. In contrast, the techniques described herein assumethat these syndromes will be different across all hardwareimplementations and thus must be dynamically learned through operationof the platform.

Moreover, one embodiment relies on the execution of a set of diagnosticquantum computing workloads which is at a higher level than existingapproaches that focus on the operation of physical qubits in the errorcorrection scheme. The described implementation utilizes this lowerlevel in combination with higher level algorithms.

AN EXEMPLARY NEUROMORPHIC PROCESSOR

In one embodiment of the invention, the neural network 614 is aneuromorphic processor utilizing a network of small-scale neuromorphiccores. One example of this is the energy-efficient neuromorphic chipdesigned by the assignee of the present application which mimics brainfunction by learning from various modes of feedback from itsenvironment. However, other types of neural network circuits may beused.

In one embodiment of the neural network 614, each neuron can send spikesignals to any target neuron in the same core or other cores. Thespiking activity of neurons are controlled stochastically by apseudo-random number generator (PRNG) to enable spike integration byother neurons between the inter-spike intervals. Each neuromorphic corehas an associated PRNG to enable spiking activity and time-step updatesof neurons in that core. The target neurons integrate the spikes as theyarrive through the Network on Chip (NoC) between their inter-spikeintervals as determined by the PRNG associated with each core. With thisapproach, neurons spike in free-running fashion while the incomingspikes are integrated in an event-driven manner.

FIG. 9 illustrates an example neuromorphic computer which employs spikebuffers 902 to store the incoming spikes in a core 900 and a controllertriggers the spike integration and spike generation activities for allthe neurons 903 in that core. Each spike buffer is coupled to an axon905 and neuromorphic cores 900 are interconnected via routers 901. Eachentry in the spike buffer 902 contains the input spikes to theneuromorphic core for one timestep. Within each timestep, all the inputspikes are integrated. Once all the neurons 903 in the entire spikingneural network have completed integration and thresholding, the networkproceeds to the next timestep.

FIG. 10 illustrates another embodiment of a neuromorphic chip which usesa scalable free-running network of neuromorphic cores 1000 to buildmassively interconnected large-scale neuromorphic computers. The spikingactivity of neurons 1002 in a core are controlled stochastically by aspike controller 1010 such that each neuron 1002 gets a chance to spikewithin a time step. Stochasticity in the firing time reduces spikecollisions in the neuromorphic computer.

By way of example, and not limitation, FIG. 9 illustrates a neuromorphiccore 1100 with M neurons 1002 and M×N synapse array 1101, where N is thenumber of fan-in connections for a neuron. In one embodiment, the spikecontroller 1010 generates a trigger signal for a neuron 1002 selectedrandomly within a core (e.g., neuron N1) and the neuron generates aspike upon threshold comparison. The outgoing spikes may be routed backinto the neuromorphic core 1000 and/or routed to neurons in otherneuromorphic cores via router 1001. When the trigger signal 1011 is atlogic low, the neurons 1002 in the core keep integrating the incomingspikes as they arrive. Once the neuron Ni generates a spike asdetermined by the trigger signal and threshold comparison, the spikepacket is then sent to the target neuron(s), where the spike isintegrated and membrane potential is updated. By adjusting the intervalof the trigger signal 1011 generated from the spike controllers 1010,the free-running network enables the neurons to perform spikeintegration as the incoming fan-in spikes are received. In oneembodiment, the pseudo-random number generator (PRNG) in the spikecontroller 1010 controls the trigger signal 1111 generation such thatthe collisions in the network are minimal (i.e., because of therandomness inserted via the PRNG). Even if there are collisions, thestochastic nature of PRNG ensures that the collisions are not periodicand appear as noise in the network. The network can be configured toeither drop or block the residual collisions that happen after adjustingthe interval of trigger signal 1111 generation using the PRNG. The spikeintegration of all fan-in spikes for a particular neuron is performedwithin its spiking interval as determined by the trigger signal'sfrequency. This approach mitigates the need to deploy spike buffers tostore incoming fan-in spikes and performs spike integration on-the-flyas they are received.

One embodiment of a spike controller and neuron group in a neuromorphiccore is illustrated in FIG. 12. The leaky integrate-and-fire neuronmodel is used in neuromorphic core shown in FIG. 12. One of the keycomponents of the spike controller 1210 is a pseudo-random numbergenerator 1201. In the illustrated implementation, a comparator 1202compares the random number generated by PRNG 1201 with a reference value1203 and when the random number is lower than the reference value, thetrigger signal 1211 is asserted high. The periodicity of PRNG is set toa high value when compared to the reference value 1203 to ensure thatthe interval between subsequent trigger signal assertions is low enoughto enable ample duration for spike integration by integration circuitry1211 by all the neurons.

In one embodiment, when the trigger signal 1210 is asserted high, acounter 1205 in the spike controller 1210 is incremented, which in turnselects a neuron 1202 in the core 1200. The counter width (q) may be setaccording to the number of neurons in the core (e.g., N=2q) and thecounter value 1205 is used as the address to select a neuron from thegroup. To add more stochasticity in neuron spiking activity, a randomoffset 1206 may be mixed with the counter value 1205 such that the orderof spiking activity in a neuromorphic core is random across differenttime steps.

Once the trigger signal 1211 is asserted high, the neuron selected byspike controller 1210 undergoes thresholding, spike generation if themembrane potential is larger than the threshold, and timestep updateprocesses, as implemented by threshold/leak/bias circuit 1210. The spikepacket 1220 is then transferred to all the fan-out connections alongwith the spiking neuron's address 1221 (counter value and core ID). Ifthe membrane potential is lower than threshold, the neuron undergoes aleak operation via threshold/leak/bias circuitry 1210. When the triggersignal is at logic low, the neurons in the core integrate all theincoming spikes in the order they arrive as selected by the targetaddress 1230. During the integration process performed by integrationcircuit 1211, the corresponding weight values 1240 are added with thecurrent membrane potential (u) 1241 and written back into the sameregister. By adjusting the period of PRNG 1201 in the spike controllers1210 and setting the reference value 1203 low, the spiking activity ofneurons across the large-scale neuromorphic computer can be controlledto enable thresholding and timestep update or spike integration withvery minimal collisions in the network. As the timestep update happenslocally within a core, the embodiments described herein eliminate theneed to route global synchronization signals which results insignificant routing area and power savings.

In the above detailed description, reference is made to the accompanyingdrawings that form a part hereof, and in which is shown, by way ofillustration, embodiments that may be practiced. It is to be understoodthat other embodiments may be utilized and structural or logical changesmay be made without departing from the scope of the present disclosure.Therefore, the following detailed description is not to be taken in alimiting sense.

Various operations may be described as multiple discrete actions oroperations in turn in a manner that is most helpful in understanding theclaimed subject matter. However, the order of description should not beconstrued as to imply that these operations are necessarily orderdependent. In particular, these operations may not be performed in theorder of presentation. Operations described may be performed in adifferent order from the described embodiment. Various additionaloperations may be performed, and/or described operations may be omittedin additional embodiments. Terms like “first,” “second,” “third,” etc.do not imply a particular ordering, unless otherwise specified.

For the purposes of the present disclosure, the phrase “A and/or B”means (A), (B), or (A and B). For the purposes of the presentdisclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B),(A and C), (B and C), or (A, B, and C). The term “between,” when usedwith reference to measurement ranges, is inclusive of the ends of themeasurement ranges. As used herein, the notation “A/B/C” means (A), (B),and/or (C).

The description uses the phrases “in an embodiment” or “in embodiments,”which may each refer to one or more of the same or differentembodiments. Furthermore, the terms “comprising,” “including,” “having,”and the like, as used with respect to embodiments of the presentdisclosure, are synonymous.

Embodiments of the invention may include various steps, which have beendescribed above. The steps may be embodied in machine-executableinstructions which may be used to cause a general-purpose orspecial-purpose processor to perform the steps. Alternatively, thesesteps may be performed by specific hardware components that containhardwired logic for performing the steps, or by any combination ofprogrammed computer components and custom hardware components.

As described herein, instructions may refer to specific configurationsof hardware such as application specific integrated circuits (ASICs)configured to perform certain operations or having a predeterminedfunctionality or software instructions stored in memory embodied in anon-transitory computer readable medium. Thus, the techniques shown inthe figures can be implemented using code and data stored and executedon one or more electronic devices (e.g., an end station, a networkelement, etc.). Such electronic devices store and communicate(internally and/or with other electronic devices over a network) codeand data using computer machine-readable media, such as non-transitorycomputer machine-readable storage media (e.g., magnetic disks; opticaldisks; random access memory; read only memory; flash memory devices;phase-change memory) and transitory computer machine-readablecommunication media (e.g., electrical, optical, acoustical or other formof propagated signals—such as carrier waves, infrared signals, digitalsignals, etc.).

In addition, such electronic devices typically include a set of one ormore processors coupled to one or more other components, such as one ormore storage devices (non-transitory machine-readable storage media),user input/output devices (e.g., a keyboard, a touchscreen, and/or adisplay), and network connections. The coupling of the set of processorsand other components is typically through one or more busses and bridges(also termed as bus controllers). The storage device and signalscarrying the network traffic respectively represent one or moremachine-readable storage media and machine-readable communication media.Thus, the storage device of a given electronic device typically storescode and/or data for execution on the set of one or more processors ofthat electronic device. Of course, one or more parts of an embodiment ofthe invention may be implemented using different combinations ofsoftware, firmware, and/or hardware. Throughout this detaileddescription, for the purposes of explanation, numerous specific detailswere set forth in order to provide a thorough understanding of thepresent invention. It will be apparent, however, to one skilled in theart that the invention may be practiced without some of these specificdetails. In certain instances, well known structures and functions werenot described in elaborate detail in order to avoid obscuring thesubject matter of the present invention. Accordingly, the scope andspirit of the invention should be judged in terms of the claims whichfollow.

What is claimed is:
 1. A machine-readable medium having program codestored thereon which, when executed by a machine, causes the machine toperform the operations of: identifying a first potential correctiveresponse to the error syndrome based on an existing error correctionmodel containing data related to known corrective responses fordifferent error syndromes; causing the first potential correctiveresponse to be implemented; and if the first potential correctiveresponse corrects the error, then updating the error correction model toinclude data related to the new error.
 2. The method of claim 1 furthercomprising program code to cause the machine to perform the operationof: selecting one or more additional potential corrective responses ifthe first potential corrective response does not correct the error untilone is identified which corrects the error.
 3. The method of claim 2further comprising program code to cause the machine to perform theoperation of: re-initializing the data qbits upon reaching a thresholdnumber of attempts to identify a corrective response.